CK-S6-SP623-G【PDF 19/48 页】BOARD DEV S6 WITH TX

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Detailed Description

User SMA Global Clock Inputs

[ Figure 1-2 , callout 12 ]

The SP623 board provides two single-ended clock input SMAs that can be used for

connecting to an external function generator. These clock inputs can alternatively be used

as a differential pair. The FPGA clock pins are connected to the SMAs as shown in

Note: Jumpers should NOT be installed on AFX SEL headers J99 and J100 if these clock inputs are

used.

Table 1-7:

SMA Clock Input Connections

FPGA Pin

R25

R26

Net Name

SMA_CLK_P

SMA_CLK_N

SMA Connector

J167

J168

User LEDs (Active High)

[ Figure 1-2 , callout 13 ]

DS10 through DS17 are eight active-High LEDs that are connected to user I/O on the

FPGA as shown in Table 1-8 . These LEDs can be used to indicate status, or any other

purpose determined by the user.

Table 1-8:

User LEDs

FPGA Pin

L21

L20

M23

M21

N26

N25

L26

L25

Net Name

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED8

Reference

Designator

DS17

DS16

DS15

DS14

DS13

DS12

DS11

DS10

User DIP Switches (Active High)

[ Figure 1-2 , callout 14 ]

DIP switch SW7 provides a set of eight active-High switches that connect to user I/O on

the FPGA, as shown in Table 1-9 . These pins can be used to set control pins, or other

functions determined by the user.

SP623 Board User Guide

UG751 (v1.1) September 15, 2010

19

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